1. Field of the Invention
This invention relates generally to Sigma-Delta Analog-to-Digital Converters. More particularly, this invention relates to continuous-time or hybrid Sigma-Delta Analog-to-Digital Converters. Even more particularly, this invention relates to circuits and methods for feedback delay compensation and signal cancellation within a quantizer of Sigma-Delta Analog-to-Digital Converters.
2. Description of Related Art
Continuous-time Sigma-delta analog-to-digital modulators or converters (CT SDM ADCs) are sensitive to delays in the feedback path. The delay is introduced by the quantizer and any circuitry in the feedback path such as data weighted averaging (DWA) or digital-to-analog converter (DAC) switching delays. CT SDM ADCs are also sensitive to signal dependent delays resulting from, for example, quantizer metastability [Cherry, et al.]. Furthermore the signal dependency in DAC switch timing [Mercer] can cause an increase in clock jitter induced noise.
In Dörrer, et al., a power and area efficient implementation of a CT SDM ADC minimizes the feedback delay by incorporating the DWA within the quantizer. Unfortunately this approach puts a tight timing requirement constraint on the quantizer and limits the DAC mismatch noise shaping to relatively simple implementations such as first-order DWA. Furthermore, the quantizer metastability is only partially alleviated with a fast switched capacitor quantizer and the signal dependent DAC switch timing effects are not dealt with. All of these problems can be resolved by latching the quantizer output to a fixed delay. However, the corresponding fixed delay in the feedback will have a detrimental effect on performance and stability to the CT SDM ADC; especially with non-return to zero (NRZ) DAC pulses, where the delay is known as excess loop delay.
The effect of excess loop delay in CT SDM ADCs is compensated with the introduction of free coefficients to the modulator's loop transfer function either through a zero in the CT filter or with an additional feedback DAC. The effect of the zero is limited by the finite gain-bandwidth (GBW) of the amplifiers in the filter, while the additional DAC increases the filter output signal, effectively reducing the dynamic range of the ADC. The zero approach is costly in power as a larger GBW is required to have a robust loop while the DAC approach is costly in die area, power and dynamic range [Keller, et al.].